To provide an accurate clock signal, it is conventional for an integrated circuit to include a crystal oscillator that uses a piezoelectric resonator. Due to their compact design, the great majority of crystal oscillators are Pierce oscillators such as an oscillator 100 of FIG. 1. A crystal or piezoelectric resonator 105 has a terminal driving a gate of an NMOS transconductance amplifier transistor Mn1 and another terminal connected to its drain. A load capacitor C2 connects between the drain of transistor Mn1 and ground. Similarly, another load capacitor C1 connects between the gate of transistor Mn1 and ground. A feedback resistor Rfb connects between the gate and drain of transistor M1, which has its drain biased by a bias current from a current source IB.
An oscillation frequency ω for crystal 105 is typically specified by its manufacturer at a certain value for the load capacitance (sum of C1+C2). The gate of transistor Mn1 will then be biased at some direct current (DC) output voltage V0 minus a factor of V1 cos ωt, where V1 is the amplitude of the output voltage swing from the DC output voltage V0. Given the negative gain from the gate of transistor Mn1 to its drain, the drain voltage then equals V0+V1 cos ωt. The output voltage swing depends upon the gain (transconductance) for transistor Mn1. In general, it is desirable for the output voltage swing to be as large as possible such that the drain voltage oscillates between ground and a power supply voltage VDD that powers current source IB. To provide a maximum output swing, the V0 voltage should thus equal to one-half of the power supply voltage VDD. But another concern is power consumption, which is reduced if transistor Mn1 is operated in the subthreshold region such that its gate-to-source voltage is less than its threshold voltage. An example DC gate voltage (which is also the V0 voltage) for transistor Mn1 in subthreshold operation is 300 mV. It may thus be appreciated that maximizing output voltage swing while minimizing power consumption for amplifier 100 are at odds with each other due to the tie between the DC voltage for the gate and drain of transistor Mn1.
To decouple the DC drain and gate voltages for transistor Mn1, it is known to use a second transistor (not illustrated) such that the DC drain voltage for transistor Mn1 equals a sum of its DC gate voltage plus a gate-to-source voltage for the second transistor. The drain voltage may thus be pushed closer to the desired mid-rail level of VDD/2 while the DC gate voltage for transistor Mn1 is suitable for subthreshold operation. But the DC drain voltage then becomes dependent on the process, voltage, and temperature corner that sets the gate-to-source voltage for the second transistor. In addition, power consumption remains high. Accordingly, there is a need in the art for improved Pierce oscillators with reduced power consumption and high gain.